用四个四选一构成16选一数据选择器verilog代码
大家好，我课程设计，遇到此题，用了四个四选一加一个二四译码器，程序编好，在片选那儿出现问题（仿真时识别不出选哪个信号），希望大神赐教，谢谢。module mux4_to_1(out,i0,i1,i2,i3,s1,s0,c);
output out;
input i0,i1,i2,i3;
input s1,s0,c;
reg out;
always @(s1 or s0 or i0 or i1 or i2 or i3 or c)
begin
if(c)
case({s1,s0})
2'b00: out=i0;
2'b01: out=i1;
2'b10: out=i2;
2'b11: out=i3;
endcase
end
endmodule
module yima2_4(outa,outb,outc,outd,ina,inb,clk,rst);
output outa,outb,outc,outd;
input ina,inb,clk,rst;
reg outa,outb,outc,outd;
always @(posedge clk or negedge rst )
begin
if(!rst)
begin
{outa,outb,outc,outd}<=4'b0;
end
else
case({ina,inb})
2'b00:{outa,outb,outc,outd}<=4'b0001;
2'b01:{outa,outb,outc,outd}<=4'b0010;
2'b10:{outa,outb,outc,outd}<=4'b0100;
2'b11:{outa,outb,outc,outd}<=4'b1000;
default: {outa,outb,outc,outd}<=4'b0000;
endcase
end
mux4_to_1 u1(.c(outa));
mux4_to_1 u2(.c(outb));
mux4_to_1 u3(.c(outc));
mux4_to_1 u4(.c(outd));
endmodule
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