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Fan-Out Wafer-Level Packaging

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发表于 2023-5-20 11:07:54 | 显示全部楼层 |阅读模式
本帖最后由 往客 于 2023-5-20 11:25 编辑

The first fan-out wafer-level packaging (FOWLP) U.S. patent was filed by Infineonon October 31, 2001, and the first technical papers were also published (2006) byInfineon and their industry partners: Nagase, Nitto Denko, and Yamada. At thattime, they called it embedded wafer-level ball (eWLB) grid array. Since 2009Infineon and since 2011 Intel and STATS ChipPAC have been in volume production of packaging semiconductor devices with the FOWLP technology.Unfortunately, because of the small sizes and low performance of the packageddevices, the FOWLP did not get too much tractions. Until September 2016, afterTSMC used their InFO (integrated fan-out) technology to package the Appleapplication processor (A10), then the whole semiconductor packaging communityis excited about the FOWLP technology. This is because the chip size of A10 is> 125 mm2 and A10 is a very high-performance SoC (system-on-chip).The advantages of FOWLP over the popular PBGA (plastic ball grid array)packages with solder-bumped flip chip are (1) lower cost, (2) lower profile,(3) eliminating the substrate, (4) eliminating the wafer bumping, (5) eliminating theflip chip reflow, (6) eliminating the flux cleaning, (7) eliminating the underfill,(8) better electrical performance, (9) better thermal performance, and (10) easier togo for system-in-package (SiP) and 3D IC packaging. The advantages of FOWLPover the popular WLCSP (wafer-level chip scale package) are (1) the use of knowngood die (KGD), (2) better wafer-level yield, (3) using the best of silicon,(4) multi-chip, (5) embedded integrated passive devices, (6) more than one RDL,(7) higher pin counts, (8) better thermal performance, (9) easier to go for SiP and3D IC packaging, and (10) higher PCB-level reliability.Unfortunately, for most of the practicing engineers and managers, as well asscientists and researchers, temporary bonding and debonding of carriers, reconstituted wafer or panel, pick and place, EMC (epoxy molding compound), compression molding, PMC (post mold cure), copper revealing, organic RDLs(redistribution layers), inorganic RDLs, hybrid RDLs, warpage, chip-first and dieface-up, chip-first and die face-down, and chip-last or RDL-first are not wellunderstood. Thus, there is an urgent need, both in industry and research institute, tocreate a comprehensive book on the current state of knowledge of these keyvenabling technologies. This book is written so that readers can quickly learn thebasics of problem-solving methods and understand the trade-offs inherent inmaking system-level decisions.There are 11 chapters in this book, namely (1) Patent Issues of Fan-outWafer-Level Packaging, (2) Flip Chip Technology versus FOWLP, (3) Fan-InWafer-Level Packaging versus FOWLP, (4) Embedded Chip Packaging, (5) FOWLP:Chip-First and Die Face-Down, (6) FOWLP: Chip-First and Die Face-Up,(7) FOWLP: Chip-Last or RDL-First, (8) FOWLP: PoP (package-on-package),(9) Fan-Out Panel-Level Packaging (FOPLP), (10) 3D Integration, and (11) 3DIC Heterogeneous Integration by FOWLP.Chapter 1 briefly discusses the patent issues of FOWLP and FOPLP. The patentsimpacting the semiconductor packaging will also be mentioned.Chapter 2 presents the wafer-level flip chip technology. Emphasis is placed onwafer bumping, various substrate technologies, flip chip assembly, underfill, andreliability. Cu–Cu direct hybrid bonding is also briefly mentioned. Finally, the flipchip technology versus FOWLP is presented.Chapter 3 details the fan-in wafer-level packaging. Emphasis is placed onWLCSP, PCB assembly of WLCSP, and solder joint reliability of WLCSP.TSMC’s UFI (UBM-free integration) WLCSP will also be briefly mentioned.Finally, WLCSP versus FOWLP will be presented.Chapter 4 presents the embedded chip packaging. Emphasis is placed on chipsembedded in laminated/polyimide substrate, Si wafer, and glass panel.Chapter 5 discusses the chip-first and die face-down FOWLP. Emphasis isplaced on the demonstration of the feasibility of a SiP (system-in-package), whichconsists of four chips and four capacitors. The test chips, test package, temporarycarrier, thermal release tape, EMC, compression molding, RDLs, solder ballmounting, and dicing will be presented.Chapter 6 provides the chip-first and die face-up FOWLP. Emphasis is placed onthe demonstration of the feasibility of a large package with three RDLs for a verylarger chip. The test chip, test package, temporary glass carrier, Cu revealing,RDLs, debonding, and dicing will be discussed. The packages are then assembledon PCB and then go through thermal-cycling test and drop test.Chapter 7 presents the chip-last (or RDL-first) FOWLP. Emphasis is placed onthe reasons for chip-last FOWLP. Various methods in making the organic RDLs,inorganic RDLs, and hybrid RDLs will be examined.Chapter 8 discusses the PoP with FOWLP. Emphasis is placed on the applicationof the FOWLP method to house the application processors for smartphones in thebottom package. STATS ChipPac’s and TSMC’s PoP with FOWLP technologywill be presented.Chapter 9 provides the fan-out panel-level packaging (FOPLP). Emphasis isplaced on various methods in using PCB technology and LDI (laser direct imaging)to make the fan-out packages. The panel versus wafer and the issues of FOPLP willbe discussed.vi PrefaceChapter 10 presents the most recent developments in 3D integrations. Emphasisis placed on 3D IC packaging, 3D IC integration, and 3D silicon integration. Whoshould be making the TSV (through silicon via) will also be discussed.Chapter 11 discusses the heterogeneous integration by FOWLP. Emphasis isplaced on heterogeneous integration on organic substrates, silicon substrates, andRDL substrates. The 3D IC heterogeneous integration by FOWLP is also provided.For whom is this book intended? Undoubtedly, it will be of great interest to threegroups of specialists: (1) those who are active or intend to become active in researchand development of the key enabling technologies of FOWLP and FOPLP such astemporary bonding and debonding of carriers, reconstituted wafer or panel, EMC,compression molding, PMC, copper revealing, RDLs fabricated by polymer andcopper plating/etching, PECVD (plasma enhanced chemical vapor deposition) andcopper damascene and CMP (chemical mechanical polishing), and PCB and LDI,warpage, chip-first and die face-up, chip-first and die face-down, and chip-last orRDL-first; (2) those who have encountered practical FOWLP and FOPLP problemsand wish to understand and learn more methods for solving such problems; and(3) those who have to choose a reliable, creative, high performance, high density,low power consumption, and cost-effective FOWLP and FOPLP technique for theirproducts. This book can also be used as a text for college and graduate students whohave the potential to become our future leaders, scientists, and engineers in theelectronics and optoelectronics industry.I hope that this book will serve as a valuable reference source for all those facedwith the challenging problems created by the ever-increasing interest in FOWLPand FOPLP. I also hope that it will aid in stimulating further research and development on key enabling technologies and more sound applications to FOWLP andFOPLP products. The organizations that learn how to design and manufacturetemporary bonding and debonding carrier, molding, and RDLs in their semiconductor packaging systems have the potential to make major advances in the electronics and optoelectronics industry, and to gain great benefits in performance,functionality, density, power, bandwidth, quality, size, and weight. It is my hopethat the information presented in this book may assist in removing roadblocks,avoiding unnecessary false starts, and accelerating design, materials, process, andmanufacturing development of key enabling technologies of FOWLP and FOPLP.Palo Alto, CA, USA John H. Lau


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